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Espressif Systems /ESP32-P4 /H264_DMA /OUT_RO_PD_CONF_CH0

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Interpret as OUT_RO_PD_CONF_CH0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (OUT_RO_RAM_FORCE_PD_CH0)OUT_RO_RAM_FORCE_PD_CH0 0 (OUT_RO_RAM_FORCE_PU_CH0)OUT_RO_RAM_FORCE_PU_CH0 0 (OUT_RO_RAM_CLK_FO_CH0)OUT_RO_RAM_CLK_FO_CH0

Description

TX CH0 reorder power config register

Fields

OUT_RO_RAM_FORCE_PD_CH0

dma reorder ram power down
OUT_RO_RAM_FORCE_PU_CH0

dma reorder ram power up
OUT_RO_RAM_CLK_FO_CH0

1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data